`timescale 1ns / 1ps

module enthernet_top_tb();
`include "./ethernet_sim/mac_bfm.svh"
`include "./ethernet_sim/eth_arp.svh"
`include "./ethernet_sim/eth_ping.svh"
`include "./ethernet_sim/eth_udp.svh"

logic rst = 0;
logic [31:00]        load_parameter;

logic [07:00]        load_m_axi_tdata;
logic                load_m_axi_tvalid;
logic                load_m_axi_tready;
logic                load_m_axi_tlast;

logic [31:00]        update_paramter;
logic [07:00]        update_m_axi_tdata;
logic                update_m_axi_tvalid;
logic                update_m_axi_tready;
logic                update_m_axi_tlast;

mac_bfm mac_bfm_i();
eth_arp eth_arp_h;
eth_ping eth_ping_h;
eth_udp eth_udp_h;

reg                     clk = 0;
always
    #(1s/125_000_000/2) clk = ~clk;

reg                     clk_200m = 0;
always
    #(1s/200_000_000/2) clk_200m = ~clk_200m;

initial
begin
    rst = 0; #1us;
    rst = 1; #2us;
    rst = 0; #1us;
end

initial
begin
    eth_arp_h = new(mac_bfm_i);
    eth_ping_h = new(mac_bfm_i);
    eth_udp_h = new(mac_bfm_i);
    //#5us eth_arp_h.send_arp();
    //#5us eth_ping_h.send_ping();
    #5us eth_udp_h.send_udp(32'haabbccdd, '{8'h11, 8'h22, 8'h33, 8'h44});
end

assign                  update_m_axi_tdata = load_m_axi_tdata;
assign                  update_m_axi_tvalid = load_m_axi_tvalid;
assign                  update_m_axi_tlast = load_m_axi_tlast;
assign                  load_m_axi_tready = update_m_axi_tready;

enthernet_top #
(
    .C_CLK_FREQ_HZ          (    125_000_000                       ),
    .LOCAL_MAC_ADDR         (    48'hC400C4010102                  ),
    .LOCAL_IP_ADDR          (    {8'd192, 8'd168, 8'd1, 8'd102}    ),
    .LOCAL_UDP_PORT         (    16'd4444                          ),
    .REMOTE_UDP_PORT        (    16'd6666                          )
)
enthernet_topEx01
(
    .clk                    (    clk                               ),
    .clk_200m               (    clk_200m                          ),
    .rst                    (    rst                               ),
    .load_parameter         (    load_parameter                    ),
    .load_m_axi_tdata       (    load_m_axi_tdata                  ),
    .load_m_axi_tvalid      (    load_m_axi_tvalid                 ),
    .load_m_axi_tready      (    load_m_axi_tready                 ),
    .load_m_axi_tlast       (    load_m_axi_tlast                  ),
    .update_paramter        (    update_paramter                   ),
    .update_m_axi_tdata     (    update_m_axi_tdata                ),
    .update_m_axi_tvalid    (    update_m_axi_tvalid               ),
    .update_m_axi_tready    (    update_m_axi_tready               ),
    .update_m_axi_tlast     (    update_m_axi_tlast                ),
    .phy_resetn             (    mac_bfm_i.phy_resetn              ),
    .gmii_tx_clk            (    mac_bfm_i.gmii_tx_clk             ),
    .gmii_txd               (    mac_bfm_i.gmii_txd                ),
    .gmii_tx_en             (    mac_bfm_i.gmii_tx_en              ),
    .gmii_tx_er             (    mac_bfm_i.gmii_tx_er              ),
    .gmii_rx_clk            (    mac_bfm_i.gmii_rx_clk             ),
    .gmii_rxd               (    mac_bfm_i.gmii_rxd                ),
    .gmii_rx_dv             (    mac_bfm_i.gmii_rx_dv              ),
    .gmii_rx_er             (    mac_bfm_i.gmii_rx_er              )
);

endmodule

